Renesas Electronics /R7FA2A1AB /SDADC24 /PGAC4

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Interpret as PGAC4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00000)PGAGC0 (others)PGAOSR 0PGAOFS0 (Reserved)Reserved 0 (0)PGAPOL 0 (0)PGASEL 0PGACTM0 (000)PGACTN 0 (00)PGAAVN 0 (00)PGAAVE 0 (0)PGAREV 0 (Reserved)Reserved 0 (0)PGACVE 0 (0)PGAASN

PGASEL=0, PGAPOL=0, PGAOSR=others, PGAGC=00000, PGAASN=0, PGACVE=0, PGAAVE=00, PGAREV=0, PGAAVN=00, PGACTN=000

Description

Input Multiplexer 4 Setting Register

Fields

PGAGC

Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal )

0 (others): Settings are prohibited.

0 (00000): (1, 1, 1)

1 (00001): (1, 2, 2)

2 (00010): (1, 4, 4)

3 (00011): (1, 8, 8)

4 (00100): (2, 1, 2)

5 (00101): (2, 2, 4)

6 (00110): (2, 4, 8)

7 (00111): (2, 8, 16)

8 (01000): (3, 1, 3)

9 (01001): (3, 2, 6)

10 (01010): (3, 4, 12)

11 (01011): (3, 8, 24)

12 (01100): (4, 1, 4)

13 (01101): (4, 2, 8)

14 (01110): (4, 4, 16)

15 (01111): (4, 8, 32).

16 (10000): (8, 1, 8)

17 (10001): (8, 2, 16)

18 (10010): (8, 4, 32)

PGAOSR

Oversampling ratio select

0 (000): 64

0 (others): Settings are prohibited.

1 (001): 128

2 (010): 256

3 (011): 512

4 (100): 1024

5 (101): 2048

PGAOFS

Offset voltage select

Reserved

This bit is read as 0. The write value should be 0.

PGAPOL

Polarity select

0 (0): Positive-side single-end input

1 (1): Negative-side single-end input

PGASEL

Analog Channel Input Mode Select

0 (0): Differential input mode

1 (1): Single-end input mode

PGACTM

Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN

PGACTN

Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN

0 (000): 0

1 (001): 1

2 (010): 2

3 (011): 3

4 (100): 4

5 (101): 5

6 (110): 6

7 (111): 7

PGAAVN

Selection of the number of data to be averaged

0 (00): 8

1 (01): 16

2 (10): 32

3 (11): 64

PGAAVE

Selection of averaging processing

0 (00): Do not average the A/D conversion results

1 (01): Do not average the A/D conversion results

2 (10): Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs

3 (11): Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times).

PGAREV

Single-End Input A/D Converted Data Inversion Select

0 (0): Do not invert the conversion result data

1 (1): Invert the conversion result data

Reserved

This bit is read as 0. The write value should be 0.

PGACVE

Calibration enable

0 (0): Do not calculate the calibration correction factor

1 (1): Calculate the calibration correction factor

PGAASN

Selection of the mode for specifying the number of A/D conversions in ADSCAN

0 (0): Specify 1 to 8,032 times by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits

1 (1): Specify 1 to 255 times linearly by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits

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